Silicon semiconductor substrate and its manufacturing method

ABSTRACT

The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a &lt;110&gt; orientation on the main surface.

TECHNICAL FIELD

The present invention relates to a single crystal silicon semiconductorsubstrate used in fabrication of a semiconductor integrated circuitdevice and a method for manufacturing the same.

BACKGROUND ART

A gate insulating film of an MISFET (Metal Insulator Semiconductor FieldEffect Transistor) fabricated using a single crystal silicon waferrequires a high performance electric characteristics such as a lowleakage current characteristic, a low interface state density and a highresistance to ion implantation and a high reliability. The main streamin techniques for forming a gate insulating film satisfying therequirements is a technique for formation of a silicon dioxide film(hereinafter also simply referred to as an oxide film) using a thermaloxidation. This technique is a so-called MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor). With the thermaloxidation, in a case where a silicon wafer with a {100} plane as a mainsurface thereof, a good oxide film of a silicon interfacecharacteristic, a dielectric breakdown voltage characteristic and aleakage current characteristic can be ensured. A major reason why asilicon wafers with a {110} plane or a {111} plane other than the {100}plane as a main surface is not used as a substrate of an integratedcircuit device is that an interface state density of an oxide filmformed on the {110} plane or the {111} plane is high. A wafer with ahigh interface state density is poor in electric characteristics such asa dielectric breakdown voltage characteristic and a leakage currentcharacteristic.

Hence, a silicon wafer substrate on which MOSFETs are fabricated hasbeen a wafer having a main surface having a {100} plane or an inclinedplane with an off-angle of about 4 degrees against the {100} plane.

In a semiconductor device fabricated on a substrate having a {100} planeas a main surface, however, there has been a problem that a p-type FEThas current driving ability, that is carrier mobility, about 0.3 time aslarge as an n-type FET. In recent years, there has been developed amethod for forming a good quality insulating film without dependence ona plane orientation of a silicon wafer, that is a radical oxidationmethod, or a radical nitriding method (2000 Symposium on VLSITechnology, Honolulu, Hi., June 13 to 15, 2000, “Advanced of RadicalOxidation for Improving Reliability of Ultra-Thin Gate Oxide”). Withthis method applied, a good insulating film can be formed on a wafersurface with a plane other than {100}.

Hence, there is highly feasible a semiconductor integrated circuitdevice fabricated using a silicon semiconductor substrate having a {110}plane as a main surface thereof on which a carrier mobility in a channeldirection of MOSFET may be raised. The inventors fabricated asemiconductor device having a main surface of the {110} plane andevaluated characteristics thereof, whereby various kinds of findingswere obtained.

The current driving ability of the above p-type FET on a substrate witha {110} plane is increased against the one on a substrate with a {100}plane by about 2.5 times, while the current driving ability of then-type FET on a substrate with a {110} plane is reduced against the oneon a substrate with a {100} plane, which is contrary to expectation. Ifthe electron mobility in the n-type FET can be raised to a value equalto or more than that in a {100} plane, a semiconductor integratedcircuit device using a substrate with a {110} plane will be practicallyand widely used.

There have effects on carrier mobility impurity scattering, phononscattering (lattice vibration scattering), and surface roughnessscattering. When the influences of these scattering are large, thecarrier mobility is decreased. Electron mobility on a surface with a{100} plane is greatly affected by roughness of a silicon surface and ithas been made definite that the worse the roughness, the lower theelectron mobility (T. Ohmi et al.: IEEE Trans Electron Devices, vol.137, p. 537, 1992). Thereafter, the following two methods have beenproposed for the purpose to reduce the surface roughness. That is, (1)formation of an oxide film on a surface of a semiconductor substrate inan atmosphere including oxygen radicals (M. Nagamine et al., IEDM Tech.Dig. p. 593, 1998) and (2) a cleaning method for a substrate surfaceexcept for RCA cleaning (W. Kern et al.: RCA Review, vol. 31, p. 187,1970).

In the radical oxidation adopted by the above method (1), by thesynergistic effects that the oxygen radicals, which are oxidationspecies, have a high probability of attaching to projections on asilicon surface and oxygen ions of O⁺ and O₂ ⁺ are attracted to theprojections charged negatively, the projections are conceivably oxidizedwith priority, whereby the surface roughness is reduced. By theoxidation in a conventional atmosphere of dry oxygen, the surfaceroughness is degraded by about 20%, whereas by the radical oxidation,the surface roughness is reduced by about 40%.

The above cleaning method (2) has been disclosed in JP A No. 11-057636.Since a cleaning step with an alkali solution in the RCA cleaning, whichhas conventionally been widely used, degrades the surface roughness, thecleaning method disclosed in JP A No. 11-057636 is a cleaning processincluding no alkali solution and has an ability of removing particles,organic contaminant, and metallic impurities, equal to or more than theRCA cleaning. Since this new cleaning process is constituted of 5 (five)steps, the process is hereinafter referred to as five-step cleaning forshort in the present specification.

The reason why the surface roughness is degraded in a cleaning stepincluding an alkali solution in the RCA cleaning is that a portion witha weak Si—Si bond is preferentially etched by hydroxide ions (OH ions).

Of the above two methods for decreasing the surface roughness, theradical oxidation method (1) is a method for reducing the surfaceroughness, whereas the five step cleaning (2) is a method forsuppressing roughening in the RCA leaning rather than a method forreducing a surface roughness. In fact, while the surface roughness isdegraded by about 50% in the conventional RCA cleaning, the five stepcleaning can restrict degradation of the surface roughness to 0% to 10%.

Since the surface roughness is reduced by the radical oxygen method, thesurface roughness can be further reduced by repetition of the radicaloxidation prior to formation of a gate oxide film, but the repetitionmay leads to an ill effect. The radical oxidation is conducted at a lowtemperature of the order in the range of from 300° C. to 500° C. At thistemperature, an oxygen donor is formed to change electric resistivity inthe interior of a substrate. If oxidation is performed at a temperatureof 500° C. or higher, formation and growth of oxygen precipitationnuclei also occur in a surface layer of a substrate, which leads leakagecurrent and dielectric breakdown of a gate oxide film.

To decrease the surface roughness of a silicon semiconductor substrateis to planarize the surface thereof at an atomic level. A mirrorpolished and cleaned surface of a silicon wafer having a specificcrystal plane has numberless irregularities at an atomic level, whichlead to surface roughness called microroughness. The microroughness isformed by generation of many microfacets different from the cuttingplane by a chemical reaction of a chemical solution used in polishingand cleaning with a silicon surface.

Since a silicon wafer sliced so as to have a {111} plane as a cuttingplane is easy to form a planar surface at an atomic level since a {111}plane itself is a facet plane. Y. J. Chabal et al. have publiclyreported that dangling bonds (covalent bonds without counterparts) ofsilicon atoms at a surface are stabilized at terminating portions byjoining hydrogen atoms thereto, thereby the surface being planarized (Y.J. Chabal et al., J. Vac. Sci. & Technol. Vol. A7, pp. 2104, 1989).

It has been made clear that a main surface of a substrate having a {111}plane as the main surface thereof is slightly inclined toward a [112]orientation or a [112] orientation by a few degrees, and is cleaned withan ammonium fluoride aqueous solution, whereby steps and terraces areformed on the surface at an atomic level with the result that thesurface is allowed to be flat at an atomic level (H. Sakaue et al.,Appl. Phys. Lett. Vol. 78, p. 309, 2001). There has been no report,however, that planarization of a mirror polished silicon substratehaving a {100} plane as a main surface, which has been most widely used,is realized at an atomic level only by cleaning the substrate.

There has been a report that in an epitaxial silicon semiconductorsubstrate epitaxially grown on the main surface thereof having anorientation slightly inclined from a {100} plane, the surface roughnessis reduced by forming steps and terraces on the main surface thereof (K.Izunome et al.: Jpn. J. Appl. Phys. Vol. 31, pp. L1277.1992). Besides,there has also been a report that steps and terraces are formed on asilicon semiconductor substrate by applying high temperature heattreatment in a hydrogen atmosphere to thereby reduce the surfaceroughness (O. Vatel et al,: Jpn, J, Appl. Phys. Vol. 32, pp. L1489,1993). There has been no report, however, on planarization of a surfacewith a {100} plane at an atomic level to which the present inventors payattention.

There have been many reports on planarization of a surface with a {100}plane by heat treatment under an ultra-high vacuum. It is difficult tointroduce such a technique into a manufacturing process for a largediameter silicon substrate with a diameter of 200 mm or larger becauseof scale-up of a heat treatment furnace and decrease in productivity.

In aspects of manufacture and supply of silicon semiconductorsubstrates, an improvement on the surface roughness by the radicaloxidation increases the number of the steps to thereby reduceproductivity. In the current silicon substrate manufacturing process, itis general to adopt a process to apply the RCA cleaning after mirrorpolishing. Hereinafter, a silicon semiconductor substrate that ispolished and cleaned is referred to as a mirror polished siliconsemiconductor substrate. A silicon semiconductor substrate as a generalterm collectively includes an epitaxial silicon semiconductor substrateand the like. The surface roughness of a mirror polished siliconsemiconductor substrate has a root mean square roughness (Rms) of theorder of 0.12 nm. A device maker fabricating semiconductor integratedcircuit devices applies the RCA cleaning to a silicon semiconductorsubstrate after accepting it. As described above, the RCA cleaningtreatment generally leads to degradation of the surface roughness.

The Rms of a silicon semiconductor substrate after RCA cleaning indevice makers is generally on the order of 0.18 nm. In a case where, inorder to form a gate oxide film on the substrate, an oxide film with athickness of the order of 5 nm is formed in a conventional dry oxygenatmosphere, the Rms of the interface is degraded to 0.22 nm. On theother hand, in a case where an oxide film with a thickness of the orderof 5 nm is formed by radical oxidation after the radical sacrificeoxidation, the Rms is of the order of 0.08 nm, thereby the surfaceroughness being greatly reduced. While it could also be one method fordecreasing the surface roughness to introduce the radical sacrificeoxidation step into a silicon semiconductor substrate maker, it leads toincrease in number of steps with reduction in productivity. Accordingly,in a case of manufacturing a silicon semiconductor substrate used infabrication of a semiconductor integrated device, it is necessary tomanufacture a silicon semiconductor substrate low in surface roughnesswithout applying sacrifice oxidation such as radical oxidation orspecial cleaning.

DISCLOSURE OF THE INVENTION

The present invention has been made in order to manufacture a siliconsemiconductor substrate used for a semiconductor integrated circuitdevice, higher in carrier mobility, especially in electron mobility,which is a carrier of an n-type FET, on a {100} plane as a main surface,and it is an object of the invention to provide a silicon semiconductorsubstrate and a method for manufacturing the same, wherein theconventional RCA cleaning is employed without the use of specialcleaning such as the five step cleaning and the surface of the substrateis planarized at an atomic level to thereby decrease the surfaceroughness thereof without the use of the radical oxidation.

In order to achieve the above object, a first aspect of a siliconsemiconductor substrate of the present invention is a siliconsemiconductor substrate comprising: a {110} plane or a plane inclinedfrom a {110} plane as a main surface of the substrate; and stepsarranged at an atomic level along a <110> orientation on the mainsurface. The plane inclined from the {110} plane is preferably a planeinclined from the {110} plane toward a <100> orientation.

The greatest feature of employing a silicon semiconductor substrate witha {110} plane or a plane inclined from a {110} plane as a main surfacein a semiconductor integrated circuit device is that hole mobility in ap-type FET in a <110> orientation is higher than in a case of a {100}plane by about 2.5 times. Therefore, in a semiconductor integratedcircuit device in which electron mobility of an n-type FET in any ofthese silicon semiconductor substrates is increased to a value higherthan electron mobility of the {100} plane, by forming a channeldirection in which electrons and holes flow in the <110> orientation,miniaturization of a circuit device can be further realized. However, itis the current state of the art that a silicon semiconductor substratehaving the {110} plane with no step at an atomic level in the <110>orientation as a main surface has a surface roughness that is not alevel equal to or less than surface roughness of the {100} plane andelectron mobility thereof is less than that of the {100} plane.

In order to decrease surface roughness, surface planarization at anatomic level is required. By making steps on a surface, terraces areformed between the steps and each terrace surface is a flat surface atan atomic level. By making an edge of the step in a <110> orientation,carriers flowing along the <110> orientation flow directly under a flatterrace surface or flow without suffering scattering due to a leveldifference between the steps, thereby an influence of scattering due tosurface roughness being decreased and high mobility being realized.Incidentally, the edge of the step is not linear at an atomic level withirregularities by a few atoms, the portion being called a kink.Therefore, the step along the <110> orientation means a step arrangedalong the <110> orientation with a magnitude of the micrometer order.

In the first aspect of a silicon semiconductor substrate of the presentinvention, a silicon single crystal thin film can be formed by means ofan epitaxial growth method on a surface of the silicon semiconductorsubstrate having a plane inclined from a {110} plane as a main surface.A silicon semiconductor substrate with a silicon single crystal thinfilm formed thereon by means of the epitaxial growth method, namely anepitaxial silicon semiconductor substrate, is hereinafter also referredto as an epitaxial silicon semiconductor substrate of the presentinvention.

Epitaxial growth on a silicon semiconductor substrate has been explainedin a model where silicon atoms are piled up at kinks of steps formed onterraces to thereby grow the steps two-dimensionally. On a surface of amirror polished silicon semiconductor substrate having a {110} plane asa main surface without slight inclination in an as-polished and cleanedstate, terraces and steps are not formed by ordinary RCA cleaning butnumberless microfacets are present. This is a primary factor ofdegradation in surface roughness. When performing epitaxial growth onthe surface, numberless microfacets play a role as kinks, thereby thesilicon atoms being piled up uniformly. Therefore, the steps andterraces arranged along a <110> orientation are not formed.

In a case of an epitaxial silicon semiconductor substrate of the presentinvention, though a main surface of a mirror polished siliconsemiconductor substrate prior to epitaxial growth is a surface slightlyinclined from a {110} plane, terraces and steps are not observed, butwhen the surface is subjected to the epitaxial growth with siliconatoms, terraces and steps are formed in the course of the growth. Sincethe surface of a terrace is flat at an atomic level, a surface roughnessis improved. A mirror polished silicon semiconductor substrate withslight inclination has a latent cause of forming terraces and steps. Byslightly inclining a main surface of a substrate toward a <100>orientation, steps are generated in parallel to a <110> orientation inwhich carriers flow, so that carriers may be flowed directly under theterrace surfaces that are flat surfaces each between the steps. Hence,no scattering of carriers occurs due to level differences of the steps.

In the first aspect of a silicon semiconductor substrate of the presentinvention, the silicon semiconductor substrate having the plane inclinedfrom the {110} plane toward the <100> orientation as the main surfacecan also be subjected to heat treatment in a hydrogen gas atmosphere, anargon gas atmosphere or an atmosphere of a mixture thereof (hereinafterthis substrate may be referred to as a heat treated siliconsemiconductor substrate). In a silicon substrate having the slightlyinclined {110} plane as a main surface, heat treated at high temperaturein the hydrogen gas atmosphere, argon gas atmosphere or the atmosphereof a mixture of both gases, there are also formed steps and terraces onthe surface of the substrate by rearranging silicon atoms on the surfacein the high temperature treatment. By selecting the <100> orientation asa direction of the slight inclination, steps are generated in parallelto a <110> orientation in which carriers flow, so that carriers can beflowed directly under the terrace surfaces each of which is a flatsurface between the steps. Hence, no scattering of carriers occurs dueto level differences of the steps either.

A second aspect of a silicon semiconductor substrate of the presentinvention is a silicon semiconductor substrate having a plane inclinedfrom a {110} plane toward a <100> orientation as a main surface and thesurface thereof is mirror polished (hereinafter the siliconsemiconductor substrate may be referred to as a mirror polished siliconsemiconductor substrate). As described above, the silicon substratehaving the plane inclined from the {110} plane toward the <100>orientation the surface of which is as polished and as cleaned hasneither steps nor terraces, whereas by subjecting the substrate toepitaxial growth or heat treatment in an atmosphere of hydrogen gas orargon gas, the steps and the terraces can be formed, so that a surfaceof the silicon substrate inherently has a cause of forming the steps andthe terraces. The steps and terraces can be formed in a cleaning step ora heat treating step in an early process for fabricating a semiconductorintegrated circuit device.

The slight inclination angle of the silicon semiconductor substrate ofthe present invention is preferably 0 degree or more and less than 8degrees. A surface inclined from a {110} plane by an angle of 8 degreestoward a <100> orientation is another low index plane {551}, and the{551} plane is necessary to be further slightly inclined in order toform steps and terraces thereon. Hence, a slight inclination angle ofthe substrate is preferably less than 8 degrees. With a larger slightinclination angle, a width of each of the terraces gets smaller and adensity of the steps increases. Since a level difference of a monoatomiclayer step is 0.192 nm, a calculated terrace width in a case of 8degrees is 1.36 nm, and since a level difference of diatomic layer stepis 0.394 nm, a terrace width is 2.73 nm; therefore, a terrace width anda step level difference are on the same order. With a higher stepdensity, a kink density increases and two-dimensional epitaxial growthusing the steps becomes difficult and hence neither steps nor terracesarranged in a specific direction are formed. The range of a slightinclination angle includes 0 degree due to an issue associated with anapparatus precision. When wafers are actually sliced from a crystalingot, a surface of a wafer generally has an error of the order of 10minutes from a target plane set to 0 degree because of a precision inangular setting of a cutting machine and an orientation measuringinstrument. Hence, it is extremely rare that an actual inclination angleof a wafer which has nominally an inclination angle of 0 degree becomescompletely 0 degree.

In the silicon semiconductor substrate of the present invention, it ispreferable that an orientation flat or a notch is formed in the <110>orientation. With such a construction adopted, the same inclinationdirection is ensured on front and back surfaces of each of wafers slicedfrom a single crystal ingot and hence the selection control of the frontand back surfaces of each wafer is not necessary, so that there may beremoved a risk to mistake a selection between the front and backsurfaces.

A first aspect of a manufacturing method for a silicon semiconductorsubstrate of the present invention is to manufacture the siliconsemiconductor substrate of the first aspect of the present invention,which comprises the steps of: preparing a silicon semiconductorsubstrate having a plane inclined from a {110} plane toward a <100>orientation as a main surface; and growing a silicon single crystal thinfilm by means of an epitaxial growth method on the main surface.

A second aspect of a manufacturing method for a silicon semiconductorsubstrate of the present invention is to manufacture the siliconsemiconductor substrate of the first aspect of the present invention,which comprises the steps of: preparing a silicon semiconductorsubstrate having a plane inclined from a {110} plane toward a <100>orientation as a main surface and heat treating the siliconsemiconductor substrate in an atmosphere of hydrogen, argon or a mixturethereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an AFM image showing steps and terraces formed on a surface ofan epitaxial silicon semiconductor substrate with a slight inclinationangle of 0.1 degree in Example 1.

FIG. 2 is a schematic view of FIG. 1.

FIG. 3 is an AFM image showing steps and terraces formed on a surface ofan epitaxial silicon semiconductor substrate with a slight inclinationangle of 7.9 degrees in Example 1.

FIG. 4 is a schematic view of FIG. 3.

FIG. 5 is an AFM image showing steps and terraces formed on a surface ofa silicon semiconductor substrate heat treated in a hydrogen atmospherewith a slight inclination angle of 0.1 degree of the present invention.

FIG. 6 is a schematic view of FIG. 5.

FIG. 7 is an explanatory view showing the fact that front and backsurfaces of a silicon semiconductor substrate of the present inventionare equivalent to each other by forming an orientation flat in a <110>orientation.

FIG. 8 is an explanatory view showing the fact that when an orientationflat is formed in a <100> orientation, front and back surfaces of asilicon semiconductor substrate of the present invention are notequivalent to each other and hence the selection control of the frontand back surfaces is necessary.

FIG. 9 is a graph showing dependence on a slight inclination angle of asurface roughness (Rms) of each of an epitaxial silicon semiconductorsubstrate and a mirror polished silicon semiconductor substrate of thepresent invention in Example 1.

FIG. 10 is a graph showing dependence on a slight inclination angle of asurface roughness (Rms) of a heat treated silicon semiconductorsubstrate of the present invention in an atmosphere of hydrogen inExample 2.

BEST MODE FOR CARRYING OUT THE INVENTION

Description will be given of embodiments of the present invention belowbased on the accompanying drawings and it is needless to say that theexamples shown in the figures are presented by way of illustration onlyand various modification or variations can be implemented as far as notdeparting from the technical concept of the present invention.

First of all, description will be given of a silicon semiconductorsubstrate according to the present invention using FIGS. 1 to 6. FIG. 1shows an AFM (Atomic Force Microscope) image of an epitaxial siliconsemiconductor substrate (W) of the present invention having a {110}plane inclined toward a <110> orientation by 0.1 degree and FIG. 2 is anschematic view of the AFM image of FIG. 1. FIG. 3 shows an AFM image ofan epitaxial silicon semiconductor substrate (W) of the presentinvention having a {110} plane inclined toward a <110> orientation by7.9 degree as a main surface and FIG. 4 is a schematic view of the AFMimage of FIG. 3. FIG. 5 shows an AFM image of a silicon semiconductorsubstrate (W) heat treated in an atmosphere of hydrogen having a planeinclined from a {110} plane toward a <110> orientation by 0.1 degree asa main surface and FIG. 6 is a schematic view of the AFM image of FIG.5.

A silicon semiconductor substrate (W) of the present invention has a{110} plane or a plane inclined from a {110} plane as a main surface,and steps (S) at an atomic level arranged along a <110> orientation onthe main surface (Examples shown in FIGS. 1 to 6 indicate the cases eachwhere a main surface is a plane inclined from a {110} plane).

In order to decrease surface roughness of the silicon semiconductorsubstrate (W), surface planarization at an atomic level is necessary. Byforming steps (S) on the silicon semiconductor substrate (W), terraces(T) are formed between the steps (S) and each surface of the terraces(T) is a planar surface at an atomic level. If the edge of the step (S)is in a <110> orientation, carriers flowing in a <110> orientation flowsdirectly under a flat surface of the terrace (T) or flows withoutscattering to be caused by the steps (S), with the result that there maybe reduced an influence of scattering from surface roughness to realizehigh mobility. Incidentally, the edge of the step (S) is not linear atan atomic level but has irregularities due to a few atoms, the portionbeing called a kink. Therefore, the steps (S) along a <110> orientationmean the steps (S) on the average with a magnitude of the micrometerorder arranged along a <110> orientation.

In order to enhance carrier mobility in a semiconductor integratedcircuit device formed on a surface of a {110} plane or a surfaceinclined from a {110} plane, there is necessarily planar at an atomiclevel the surface in a <110> orientation in which carriers flow. Ifsteps can be formed averagely along a <110> orientation on a surface ofthe silicon semiconductor substrate having a {110} plane or a planeinclined from a {110} plane as a main surface, carriers can flow in a<110> orientation directly under planar surfaces of terraces generatedbetween the steps. An epitaxial silicon semiconductor substrate of thepresent invention is contrived in order to form steps in a <110>orientation and prepared by forming a silicon single crystal thin filmin epitaxial growth on the surface of the mirror polished siliconsemiconductor substrate having a plane inclined from the {110} planetoward the <100> orientation as the main surface.

Then, description will be given of forming an orientation flat or anotch in the <110> orientation on a silicon semiconductor substratehaving a plane inclined from a {110} plane toward in a <100> orientationas a main surface using FIG. 7. FIG. 7 is an explanatory view showingthe fact that front and back surfaces of a silicon semiconductorsubstrate of the present invention are equivalent to each other byforming an orientation flat in a <110> orientation. One effect of thepresent invention is not to necessitate selection of a front or backsurface of the silicon semiconductor substrate. In FIG. 7, there isshown a case where a {110} plane of the silicon semiconductor substrateis specified as the (110) plane and an orientation flat OF (since thecontext here applies to a case of a notch, an orientation flat is,hereinafter, adopted for description) is formed in the [{overscore(1)}10] orientation. When an axis in the [110] orientation (the arrowmark OA) perpendicular to the (110) plane is inclined toward the [001]orientation, the axis changes to a new axis shown the arrow mark OA′ inthe figure. Thereby, a main surface changes to a plane perpendicular tothe new arrow mark OA′. In a case where the wafer is turned upside downand the back surface side is polished, an inclination orientation of theback surface is an arrow mark OA″ shown on the back surface side and isthe same direction as the orientation flat OF. In other words, aninclination direction on the basis of the orientation flat OF is thesame direction in respect of turnover between the front and backsurfaces. Therefore, in a fabrication process for a siliconsemiconductor substrate, there can be provided a silicon semiconductorsubstrate with a crystallographically equivalent structure on the basisof the orientation flat OF without selection of a front or back surface.

For comparison, FIG. 8 shows a case where an orientation flat of thesilicon semiconductor wafer (W) is formed in the [001] orientation. Inthe same way as FIG. 7, when an axis in the [110] orientation (the arrowmark OA) perpendicular to the (110) plane is inclined toward the [001]orientation, the axis changes to a new axis shown the arrow mark OA′ inthe figure. Thereby, a main surface changes to a plane perpendicular tothe new arrow mark OA′. In a case where the wafer is turned upside downand the back surface side is polished, an inclination orientation of theback surface is an arrow mark OA″ shown on the back surface side and isthe direction rotated by 180 degrees against the orientation flat OF. Awafer has an inclination orientation inclined toward the direction([001]) of the orientation flat, while another wafer has an inclinationorientation inclined toward the direction opposite to the direction([001]) of the orientation flat. Therefore, in a device fabricationprocess for fabricating a semiconductor device where siliconsemiconductor substrates are aligned in a direction on the basis of anorientation flat and subjected to various treatment, there is present amixture of wafers having inclination orientations different by 180degrees, so that devices with the same characteristic cannot befabricated.

A first aspect of a method for manufacturing a silicon semiconductorsubstrate of the present invention comprises the steps of: preparing asilicon semiconductor substrate having a plane inclined from a {110}plane toward a <100> orientation as a main surface; and growing asilicon single crystal thin film by means of an epitaxial growth methodon the main surface. Using the above method, the silicon semiconductorsubstrate of the present invention is manufactured.

A second aspect of a method for manufacturing a silicon semiconductorsubstrate of the present invention comprises the steps of: preparing asilicon semiconductor substrate having a plane inclined from a {110}plane toward a <100> orientation as a main surface; and heat treatingthe silicon semiconductor substrate in an atmosphere of hydrogen, argonor a mixture thereof. Using the above method, the silicon semiconductorsubstrate of the present invention is manufactured.

EXAMPLES

While further detailed description will be given of the presentinvention using Examples below, and it is needless to say that theExamples are presented by way of illustration only and not to beconstrued by way of limitation.

Example 1

Wafers were manufactured by slicing a silicon single crystal pulled inthe [110] orientation in the states inclined toward the [001]orientation by 0 degree, 0.1 degree, 1.0 degree, 2.0 degrees, 4.0degrees, 6.0 degrees, 7.9 degrees and 10.0 degrees. The crystal wasboron doped and of a p-type. Electric resistivity thereof was in therange of from 10 to 12 Ωcm. A diameter thereof was 150 mm. Sliced waferswere processed into mirror polished wafers by the use of ordinarychemical mechanical polishing and thereafter, they were subjected to RCAcleaning. Epitaxial growth was carried out on the mirror polishedsilicon semiconductor substrates to form a silicon single crystal thinfilm with a thickness of about 5 μm. Trichlorosilane (SiHCl₃) wasemployed as a raw material gas and the thin film was grown in a hydrogenatmosphere at a reaction temperature of 1130° C.

Measurement of surface roughness was implemented with SPA360manufactured by SEIKO INSTRUMENTS Co. capable of measuring unevenness ona surface using a function of AFM (Atomic Force Microscope) and thesurface roughness thus obtained was expressed in Rms. In FIG. 9, thereis shown dependence on a slight inclination angle of Rms of an epitaxialsilicon semiconductor substrate. For comparison, data of mirror polishedsilicon semiconductor substrates with respective inclination angles arealso shown therein. In a case of a slight inclination angle of 0 degree,Rms of a mirror polished silicon semiconductor substrate and Rms of anepitaxial silicon semiconductor substrate are 0.118 nm and 0.112 nm,respectively.

Incidentally, Rms=0.118 nm of a mirror polished silicon semiconductorsubstrate having a {110} plane without inclination as a main surface isalmost the same as Rms of a mirror polished semiconductor substratehaving a {100} plane without inclination as a main surface. Surfaceroughness of an epitaxial silicon semiconductor substrate with a slightinclination angle of even 0.1 degree is reduced to the value lower thanthat of a mirror polished silicon semiconductor substrate. An effect ofthe reduction is recognized at least to the inclination angle of 7.9degrees. Since a level difference of a monoatomic layer step on a {110}plane as a main surface is 0.192 nm, the width of a terrace in a case of7.9 degrees is 1.38 nm by calculation, and since a level difference of adiatomic layer step is 0.394 nm, the width of a terrace is 2.76 nm;therefore, a terrace width and a step level difference are on the sameorder. As step spacing is narrower, a step density is higher; a kinkdensity is higher and hence two-dimensional epitaxial growth caused bythe steps is more difficult. With 10.0 degrees, surface roughness isdegraded.

FIG. 1 shows an AFM image of surface roughness of an epitaxial siliconsemiconductor substrate with a slight inclination angle 0.1 degree andFIG. 2 shows a schematic view of FIG. 1. As shown in FIGS. 1 and 2,there can be recognized steps (S) and terraces (T). A step (S) is onaverage formed in a <110> orientation. The width of the terrace (T) isabout 100 nm. The width (L) of the terrace (T) can be predicted using aformula established between a level difference (h) of a step (S) and aslight inclination angle (a) in a simplified model: tan α=h/L. In a caseof {110}, the level difference of the monoatomic layer step is 0.192 nmand the level difference of the diatomic layer step is 0.384. When theslight inclination angle is 0.1 degree, a terrace width betweenmonoatomic layer steps is 110 nm. This value agrees with the prediction.When the slight inclination angle exceeds 1 degree, a terrace widthbetween monoatomic layer steps is estimated 10 nm or less.

It is difficult to observe the steps and terraces in this case with AFM.Since the surface roughness Rms is lower than that of a mirror polishedsilicon semiconductor substrate, it is considered that the steps andterraces are formed. Thus, it is predicted that the larger the slightinclination angle, the smaller the terrace width, whereas exception isrecognized in a case of the slight inclination angle of 7.9 degrees. InFIG. 3, there is shown an AFM image in that case and in FIG. 4, there isshown a schematic view of the AFM image thereof. As clear from FIGS. 3and 4, the terrace is formed considerably wider than predicted terracewidths of 1.38 nm or 2.76 nm. While an orientation of the steps (S) ismostly a <110> orientation, the step line is curved, which means thatgrowth of the steps (S) is fluctuated. The reason why the considerablywide terrace (T) is formed is that in a case where the main surface isinclined from the {110} plane toward the <100> orientation by 7.9degrees, the main surface becomes a plane inclined from a {551} plane ofa low index plane by 0.15 degree; therefore, the main surface is a planeslightly inclined from a facet plane of the {551} plane. This ispresumed from the fact that in a case where a main surface is slightlyinclined from a {111} plane of a facet plane toward a <112> orientation,steps and terraces are formed.

Example 2

Then, description will be given of a surface roughness of a heat treatedsilicon semiconductor substrate. As in a case of an epitaxial siliconsemiconductor substrate, wafers were manufactured by slicing a siliconsingle crystal pulled in the [110] orientation in the states inclinedtoward the [001] orientation by 0 degree, 0.1 degree, 1.0 degree, 2.0degrees, 4.0 degrees, 6.0 degrees, 7.9 degrees and 10.0 degrees. Slicedwafers were processed into mirror polished wafers by the use of ordinarychemical mechanical polishing and thereafter, they were subjected to RCAcleaning. The mirror polished silicon semiconductor substrates wassubjected to heat treatment in a hydrogen atmosphere at 1150° C. for 1hr. In FIG. 10, there is shown dependence on a slight inclination angleof Rms of a silicon semiconductor substrate heat treated in a hydrogenatmosphere.

For comparison, data of mirror polished silicon semiconductor substratesare also shown therein. In a case of a slight inclination angle of 0degree, Rms of a mirror polished silicon semiconductor substrate and Rmsof a silicon semiconductor substrate heat treated in a hydrogenatmosphere are 0.118 nm and 0.111 nm, respectively. Dependence on aslight inclination angle of Rms is the same as that of an epitaxialsilicon semiconductor substrate. That is, surface roughness of a siliconsemiconductor substrate heat treated in a hydrogen atmosphere with aslight inclination angle in the range of from 0.1 degree to 7.9 degreesis reduced to the value lower than that of a mirror polished siliconsemiconductor substrate.

FIG. 5 shows an AFM image in a case of a slight inclination angle 0.1degree and FIG. 6 shows a schematic view of FIG. 5. Though the AFM imageis not clearer than in a case of an epitaxial silicon semiconductorsubstrate, steps and terraces are formed. Thus, though it can be saidthat steps and terraces are formed with difficulty more than anepitaxial silicon semiconductor substrate, surface roughness Rms of aheat treated silicon semiconductor substrate with a slight inclinationangle is reduced to the value lower than that of a mirror polishedsilicon semiconductor substrate, so that scattering of carriers due tosurface roughness can be reduced.

Example 3

Description will be given below of fabrication of a semiconductor deviceon a silicon semiconductor substrate of the present invention andmeasurement of carrier mobility thereof. There were used mirror polishedsilicon semiconductor substrates having respective planes inclined from{110} planes by angles of 0 degree, 0.1 degree and 7.9 degrees as mainsurfaces, epitaxial silicon semiconductor substrates obtained by growinga silicon single crystal thin film with a thickness of 5 μm on themirror polished silicon semiconductor substrates, and heat treatedsilicon semiconductor substrates obtained by heat treating the mirrorpolished silicon semiconductor substrates in a hydrogen atmosphere. Adiameter, an electric resistivity and an oxygen concentration of themirror polished silicon substrate were 150 mm, of a p-type in the rangeof from 10 to 12 Ωcm, and 16 ppma (the JEIDA conversion), respectively.The median of the electric resistivity of the epitaxial silicon layerwas 11 Ωcm. The heat treatment in a hydrogen atmosphere was performed at1150° C. for 1 hr. A mirror polished silicon semiconductor substratehaving a {100} plane as the main surface without inclination was used asa reference sample. An electric resistivity and an oxygen concentrationthereof were almost the same as the above values. Incidentally, JEIDA isan abbreviation of Japan Electronic Industry Development Association(currently, changed to JEITA: Japan Electronic Information TechnologyIndustry Association).

In order to actually prove an effect of improving electron mobility, ann-type field effect transistor was fabricated using the abovesubstrates. A trench was at first formed thereon for the deviceisolation by means of a STI (Shallow Trench Isolation) method and buriedwith a silicon oxide film (SiO₂). Then, the substrates were subjected tothe RCA cleaning and organic materials, particles and metals wereremoved therefrom and after that, a gate oxide film with a thickness of5 nm was formed thereon in a dry oxidizing atmosphere. Boron (B) was ionimplanted all over the substrate surface in order to control a thresholdvoltage of the gate.

Next, a polycrystal silicon film was deposited all over the substratesurface by means of a CVD (Chemical Vapor Deposition) method andpatterning was carried out thereon to form a polycrystal siliconelectrode on a gate oxide film in a transistor forming area. Then,phosphorus (P) was ion implanted at a low concentration to form an n⁻source region and an n-drain region to relax a high voltage field. Adirection in which electrons flow is a <110> orientation. Then a siliconoxide film was deposited all over the substrate by the CVD method so asto cover the gate electrode and anisotropic etching was applied to thesilicon oxide film to form a sidewall insulating film on the sidewall ofthe gate electrode. Finally, arsenic was ion implanted at a highconcentration to form an n⁺ source region and an n⁺ drain region.Evaluation was performed on the electron mobility of the n-type fieldeffect transistor thus fabricated.

Table 1 shows the value of the electron mobility in each of thesubstrates against the reference value of 1 for the electron mobility inthe mirror polished silicon semiconductor substrate having a {100} planeas a main surface. The electron mobility of the epitaxial siliconsemiconductor substrate having slight inclination is 1.4 times that ofthe mirror polished silicon semiconductor substrate having the {100}plane as a main surface, which has been widely employed. Even theelectron mobility of the silicon semiconductor substrate heat treated ina hydrogen atmosphere having slight inclination is about 1.2 times. Theelectron mobility of the mirror polished silicon semiconductor substratehaving a slight inclination is about 0.8 times that of the substratehaving a {100} plane as a main surface, which is inferior, but the aboveelectron mobility is 1.3 times that of the substrate having a {110}plane with no inclination, which reveals an effect of inclination. Inthis Example, the conventional RCA cleaning was applied in thesemiconductor device fabrication process, but there is a possibility toimprove the electron mobility further by improving a cleaning method anda heat treatment method. For example, by applying the above describedfive-step cleaning or the radical sacrifice oxidation treatment, it canbe expected that the surface roughness is further improved and thecarrier mobility is also increased to a higher value. TABLE 1Inclination angles ([001] orientation) {100} Substrate 0° 0.1° 7.9°Mirror polishing 0.62 0.81 0.79 Epitaxial growth 0.76 1.46 1.44 Heattreatment 0.72 1.22 1.15

INDUSTRIAL APPLICABILITY

As described above, the silicon semiconductor substrate of the presentinvention is planarized at an atomic level, the surface roughness of thesilicon semiconductor substrate can be reduced to a value lower thanthat of the conventional silicon semiconductor substrate by about 10%,and since the surface steps at an atomic level are formed along adirection in which carriers of a semiconductor device flow, carriermobility of the semiconductor device can be improved by 40% at most ascompared with a case of the conventional silicon semiconductorsubstrate. By using the silicon semiconductor substrate of the presentinvention as a substrate of a semiconductor integrated circuit device, ahigh performance device can be realized. Moreover, according to themethod of the present invention, the silicon semiconductor substrate ofthe present invention can be effectively manufactured.

1. A silicon semiconductor substrate comprising: a {110} plane or aplane inclined from a {110} plane as a main surface of the substrate;and steps arranged at an atomic level along a <110> orientation on themain surface.
 2. The silicon semiconductor substrate according to claim1, wherein the plane inclined from the {1 10} plane is a plane inclinedfrom the {1 10} plane toward a <100> orientation.
 3. The siliconsemiconductor substrate according to claim 2, wherein a silicon singlecrystal thin film is formed by means of an epitaxial growth method onthe surface of the silicon semiconductor substrate having the planeinclined from the {110} plane as the main surface.
 4. The siliconsemiconductor substrate according to claim 2, wherein the siliconsemiconductor substrate having the plane inclined from the {110} planetoward the <100> orientation as the main surface is subjected to heattreatment in a hydrogen gas atmosphere, an argon gas atmosphere or anatmosphere of a mixture thereof.
 5. A silicon semiconductor substratehaving a plane inclined from a {100} plane toward a <100> orientation asa main surface, the surface thereof being mirror polished.
 6. Thesilicon semiconductor substrate according to claim 2, wherein aninclination angle of the silicon semiconductor substrate having theplane inclined from the {110} plane toward the <100> orientation as themain surface is 0 degree or more and less than 8 degrees.
 7. The siliconsemiconductor substrate according to claim 2, wherein an orientationflat or a notch is formed in the <110> orientation.
 8. A method formanufacturing a silicon semiconductor substrate, which is the siliconsemiconductor substrate according to claim 2, comprising the steps of:preparing a silicon semiconductor substrate having a plane inclined froma {1 10} plane toward a <100> orientation as a main surface; and growinga silicon single crystal thin film by means of an epitaxial growthmethod on the main surface.
 9. A manufacturing method for a siliconsemiconductor substrate, which is the silicon semiconductor substrateaccording to claim 2, comprising steps of: preparing a siliconsemiconductor substrate having a plane inclined from a {110} planetoward a <100> orientation as a main surface; and heat treating thesilicon semiconductor substrate in an atmosphere of hydrogen, argon or amixture thereof.